Bangalore, India, November 19, 2009 Magma Design Automation Inc., a provider of chip design software, today announced Hydraâ„¢ 1.1, an enhanced version of Magma‘s hierarchical design planning solution for large systems on a chip (SoCs). The new version features out-of-the-box reference flows for channel-style, near-abutment, full-abutment, black-box, repeated-block and multi-power domain methodologies, allowing designers to get started quickly and combine these various approaches easily. New advanced capabilities and enhanced ease of use enable faster delivery of better floor plans.

“For large SoCs, the traditionally manual approaches to feasibility analysis and chip planning are too inaccurate and time consuming,” said Premal Buch, general manager of Magma‘s Design Implementation Business Unit. “Hydra provides designers the ideal combination of advanced capabilities and broad flexibility, letting them apply their expertise to critical issues while Hydra automates significant portions of the hierarchical design planning flow.”

Hierarchical Flow Manager: A Faster Path to Better Floorplans

Hydra 1.1 features a hierarchical flow manager that enables designers to deliver higher quality floorplans faster. Reference flows for commonly used design styles such as channel based, near abutment and black box are available. Support for more complex flows such as full abutment, repeated block and multi-power domains that are compliant with both the Unified Power Format (UPF) and Common Power Format (CPF), is also provided. These unique reference flows can be used in any combination to obtain an optimal floorplan. They also enable design teams to perform design feasibility analysis at strategic points in the flow to evaluate early netlist quality, floorplan routability and performance goals.

Advanced Technology, Powerful Automation and High Capacity

Hydra 1.1 offers industry-leading capabilities, including:

· Automatic macro placement high quality placement of thousands of macros in just hours

· The industry‘s only concurrent cluster placement and shaping

· Exclusive slack-proportionate time budgeting and re-budgeting

· The industry‘s only truly hierarchical global routing

· The industry‘s only hierarchical clock tree planning

Hydra includes the industry‘s best macro placement. It is able to automatically place the most challenging designs in hours with excellent quality of results. The Hydra 1.1 macro placer has been enhanced to offer improved capacity with support for thousands of macros, improved congestion and timing awareness for both inter-block and intra-block communication, and extended relative placement constraint support. Hydra is the only hierarchical design planning solution that places and shapes blocks concurrently, reducing this normally time consuming manual task to just a few hours. In Hydra 1.1, the shaper has been enhanced to support any mix of design styles including channel style, near abutment and full abutment. The shaper now supports incomplete netlist specifications by taking into account black-box characteristics.

Hydra 1.1 features slack-proportionate time budgeting and incremental re-budgeting. This approach delivers more accurate budgets than traditional methods through continuous refinement based on the physical topology, timing criticality of partitions and block implementation. Hydra 1.1‘s new clock planning technology is now truly hierarchical, supporting both top-down and bottom-up clock tree construction. Hydra 1.1 also features new global routing technology with native support for hierarchy and multi-threading, resulting in faster, more accurate global routing during the chip planning stage. The new global router has support for net-specific topology control, transit region support allowing for a mixture of feed throughs and flyovers, and MVdd aware topology construction.


Hydra 1.1 is currently available. It can be used standalone or integrated within the Talus® flow. For pricing and other information, contact Magma at [email protected].

About Magma
Magma's electronic design automation (EDA) software is used to create complex, high-performance integrated circuits (ICs) for cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma products for IC implementation, analog/mixed-signal design, analysis, physical verification, circuit simulation and characterization are recognized as embodying the best in semiconductor technology, providing the world's top chip companies the "Fastest Path to Silicon."TM Magma maintains headquarters in San Jose, Calif., and offices throughout North America, Europe, Japan, Asia and India. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at

Magma and Talus are registered trademarks and Core and "Fastest Path to Silicon" are trademarks of Magma Design Automation Inc. All other product and company names are trademarks or registered trademarks of their respective companies.

Forward-Looking Statements:

Except for the historical information contained herein, the matters set forth in this press release, including statements that Talus has been used to implement more 45-/40-nm designs than other implementation systems, offers faster runtime and timing convergence, reduces area and provides higher capacity of advanced designs and other statements about the features and benefits of Magma‘s products, are forward-looking statements within the meaning of the “safe harbor” provisions of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the ability of Magma‘s products to produce the desired results and Magma‘s ability to keep pace with rapidly changing technology. Further discussion of these and other potential risk factors may be found in Magma's public filings with the Securities and Exchange Commission ( Magma undertakes no additional obligation to update these forward-looking statements.


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